Once formation of semiconductor devices and interconnects on a semiconductor wafer (substrate) is completed, the semiconductor wafer is diced into semiconductor chips, or “dies.” Functional semiconductor chips are then packaged to facilitate mounting on a circuit board. A package is a supporting element for the semiconductor chip that provides mechanical protection and electrical connection to an upper level assembly system such as the circuit board. One typical packaging technology is Controlled Collapse Chip Connection (C4) packaging, which employs C4 balls each of which contacts a C4 pad on the semiconductor chip and another C4 pad on a packaging substrate. The packaging substrate may then be assembled on the circuit board.
Thus, the packaging substrate provides an electrical link between the semiconductor chip and a system board of a computer. A semiconductor chip is mounted on a die foot print area located on a top surface of the packaging substrate. The semiconductor chip contains C4 pads on which an array of C4 balls may be attached by C4 bonding. The C4 balls are subsequently attached to the die foot print area of the packaging substrate.
A typical semiconductor chip employing a packaging substrate may comprise about 5,000 input/output nodes. Each of these nodes are electrically connected to a C4 pad on a top surface of the semiconductor chip in a two dimensional array. Typical two dimensional array configurations for the C4 pads include 4 on 8 configuration, which employs C4 solder balls having a diameter of 4 mils (approximately 100 microns) and a pitch of 8 mils (approximately 200 microns) in a rectangular array, and 3 on 6 configuration, which employs C4 solder balls having a diameter of 3.0 mils (approximately 75 microns) and a pitch of 6 mils (approximately 150 microns) in a rectangular array. Thus, more than 5,000 C4 solder balls may be formed on the semiconductor chip, which may be typically about 2.5 cm×2.5 cm in size.
The collection of metallic layers employed to attach a C4 ball to a semiconductor chip is called an “underbump metallurgy structure,” or a “UBM structure” in the art. A typical underbump metallurgy structure includes a stack of a metallic diffusion barrier layer and a wetting promotion layer. The metallic diffusion barrier layer is formed directly on the semiconductor chip and comprises an adhesion promoting metallic material such as Ti, TiW, or TiN. The wetting promotion layer may comprise an elemental metal such as Cu, Ni, Au, or Ag. Alternately, the wetting promotion layer may comprise a Cu—Ni alloy. Usable material for the wetting promotion layer is limited since the wetting promotion layer needs to provide wetting for a C4 ball to be soldered thereupon.
Electromigration resistance of C4 balls is critical in determining limits of operating temperature and electrical current that the C4 balls may be subjected to. The higher the electromigration resistance of the C4 balls, the harder it is for electromigration to occur at a given condition of electrical current and temperature, and the longer the expected lifetime of the module employing the C4 balls within the chip package. The expected lifetime of a module is typically measured in thousands of power on hours (KPOH), and typically translates to at least several years of operation in normal operation mode.
As an increasing number of input and output nodes are employed in a semiconductor module, more C4 balls are employed in the semiconductor module, which requires use of a high density array of C4 balls with reduced pitch between C4 balls. As the pitch of a C4 array decreases, for example from a 4 on 8 array to a 3 on 6 array, the diameter of the C4 ball also decreases. Since the cross-sectional area of a C4 ball shrinks with the shrinking diameter of the C4 ball, the current carrying capacity of the C4 ball also reduces with the shrinking diameter of the C4 ball. Thus, C4 balls employed in a 3 on 6 array have reduced current carrying capacity compared to C4 balls employed in a 4 on 8 array. Such a trend is expected to continue as advanced semiconductor modules employ a large number of input and output nodes.
In general, a reduction in the size of a C4 ball requires a capability to handle a higher current density in the C4 ball. In light of such requirements, the need to enhance current handling capacity of C4 balls has become imperative.
Further, elimination of aluminum pads is desirable in some semiconductor chips. In this case, the absence of aluminum pads results in reduction in heat spreading and lateral thermal and electrical conduction as a C4 ball is bonded on a copper pad. Such a configuration requires enhancement in electromigration resistance, i.e., a higher current carrying capacity for the C4 ball.
Yet further, lead-free C4 balls, which comprise Sn, Cu, and Ag, provide enhancement in intermetallic compound formation between the C4 ball and the underbump metallurgy structure, thereby causing an increase in the amount of material consumed during the reflow of the C4 ball. Such intermetallic compounds tend to create hot spots at which a local current density is higher than the surrounding region, and electromigration failure may occur at such hot spots.
In view of the above, there exists a need for an underbump metallurgy structure that provides an enhanced current carrying capacity for a C4 ball to be bonded thereupon, and methods of manufacturing the same.